Handbook of Memristor Networks

Preface

Contents

1 The Fourth Element

1 Axiomatic Definition of Circuits Elements

2 (v(?)-i(?)) Circuit Elements

3 Complexity Metric of Circuit Elements

4 Fingerprint of Memristors

5 Concluding Remarks

References

2 If It’s Pinched It’s a Memristor

1 If It’s Pinched It’s a Memristor

1.1 First Man-Made Memristor

1.2 Pre-1948 Memristors

1.3 Pre-1970 Thin Oxide-Film Memristors

1.4 1971: Synthesized Memristors

1.5 Post-2000 Memristors

1.6 Organic Memristors

1.7 Biological Memristors

1.8 Plant Memristor

1.9 A Micro Kinetic Memristor

2 Three Memristor Representations

2.1 Extended Memristor

2.2 Generic Memristor

2.3 Ideal Memristor

3 Potassium and Sodium Ion Channels Are Generic Memristors

3.1 Pinched Hysteresis Loops Evolve with Frequency

3.2 Pinched Hysteresis Loops Degenerate to Straight Lines at High Frequencies

3.3 DC V-I Curves

4 Ideal Memristors Have Bizarre DC V-I Curves

4.1 Example 1: Memristor V-I “Rectifier” Curve

4.2 Example 2: Memristor Without a DC V-I Curve

4.3 The DC V-I Curve of an Ideal Memristor Is a Single Point (V, I) = (0, 0)!

5 Ideal Memristor: Four Guided Tours

5.1 Ideal Memristor Guided Tour 1

5.2 Ideal Memristor Guided Tour 2

5.3 Ideal Memristor Guided Tour 3

5.4 Ideal Memristor Guided Tour 4

5.5 All Ideal Memristors Are Non-volatile Analog Memories

5.6 Modelling Beck et al. “Bow-Tie” Loop

6 Generic Memristor: A Guided Walk

6.1 Non-volatile Binary Memory

6.2 How to Set and Reset Memory States?

6.3 Why Minimum Pulse Width and Minimum Pulse Amplitude?

6.4 A Bi-continuum Non-volatile Memory

6.5 Pinched Hysteresis Loop Need not Be Symmetric

7 Extended Memristors: A Glimpse

8 Locally-Active Memristors

8.1 A Locally-Active Memristor Oscillator

8.2 A One-Memristor Chaos Generator

8.3 A One-Memristor Oscillator

9 If It’s Not Pinched It’s Not a Memristor

10 Concluding Remarks

Appendix

References

3 Everything You Wish to Know About Memristors but Are Afraid to Ask

1 Some Nagging Questions About Memristors

2 Experimental Definition of Memristors

3 Ideal Memristors

4 Ideal Generic Memristor

4.1 Graphical Composition Method for Generating G(X) and  (x) from a Voltage-Controlled Ideal Memristor

4.2 Graphical Composition Method for Generating R(X) and  (x) from a Current-Controlled Ideal Memristor

4.3 Ideal Memristors and Its Siblings Give Identical Pinched Hysteresis Loops

4.4 Recovering Ideal Memristor from Its Siblings

5 Generic Memristor

6 Extended Memristor

7 Pinched Hysteresis Loop Fingerprints

8 Coincident Zero-Crossing Signatures

8.1 Passive Memristors Have Identical Zero Crossings

8.2 Passive Memristors Have Zero Phase Shifts

9 POP: Power—Off Plot

10 DC V-I Plots

10.1 Passive but Locally-Active Memristors

10.2 DC V-I Plots May Contain Unobservable Points

10.3 Two Stable Branches Through Origin Implies Non-volatile Binary Memory

10.4 Quasi DC V-I Plot

10.5 A Shoelace DC V-I Plot

11 Continuum-Memory Memristors

11.1 Pinched Hysteresis Loop at Extreme Low Frequencies

11.2 Quasi DC V-I Plot Is not DC V-I Plot!

12 Concluding Remarks

Appendix

References

4 Aftermath of Finding the Memristor

References

5 Three Fingerprints of Memristor

1 Introduction

2 Generic Definition of Memristor

3 Memristor Fingerprints

3.1 Memristor Fingerprint 1: Pinched Hysteresis Loop

3.2 Memristor Fingerprint 2: Hysteresis Lobe Area Decreases as Frequency Increases

3.3 Memristor Fingerprint 3: Pinched Hysteresis Loop Shrinks to a Single-Valued Function at Infinite Frequency

4 Memductance Limiting-Slope Calculation Methods

4.1 Memductance Limiting-Slope Calculation Method 1

4.2 Memductance Limiting-Slope Calculation Method 2

5 Transversality at the Origin

5.1 Example of Transversal Pinched Hysteresis Loop

5.2 Examples of Non-transversal Pinched Hysteresis Loop

6 Conclusion

References

6 Resistance Switching Memories are Memristors

1 Pinched Hysteresis Loops

2 Continuum of Non-volatile Memories

3 -q Curve and Memristance Versus State Maps are Equivalent Memristor Representations

4 Resistance Versus State Map and State Equation

5 Correspondence Between Small-Signal Memristance and Chord Memristance

6 Ideal Memristor -q Curves for Binary Memories

7 Unfolding the Memristor

7.1 Non-volatile Memristors

7.2 Negative Resistance

7.3 Is Memristor Negative Resistance Real or Artifact?

8 Switching and Sensing Resistance Memory

9 Concluding Remarks

References

7 The Detectors Used in the First Radios were Memristors

1 Introduction

2 Cat's Whisker Detector Setup

3 Terminology

4 Experimental Results

4.1 Cohering Action

4.2 Multistable Memristive Behavior

4.3 Bistable Resistive RAM/Memristive Mode

5 Discussion

References

8 Why are Memristor and Memistor Different Devices?

1 Introduction

2 Memristor and Memistor are Different

2.1 Memristor

2.2 Memistor

3 Memristor-Based Memistor

3.1 Two Back-to-Back Series-Connected Memristors

3.2 Charge Versus Flux Relationship of the Composite Device with Two Back-to-Back Series-Connected Memristors

4 Widrow's Memistor is Not Well-Posed

5 More Distinctions Between Memistor and Memristor

6 Conclusion

References

9 The Art and Science of Constructing a Memristor Model: Updated

1 Introduction

2 Locally Active Memristor: Physical Principles Approach

3 Nonvolatile Titanium Dioxide Memristor: Measurement Approach

4 Nonvolatile Tantalum Pentoxide Memristor: State Variable Identification

5 Conclusions

References

10 Memristor, Hodgkin-Huxley, and Edge of Chaos

1 Introduction

2 Definition, Symbol, and Fingerprints

2.1 Memristor is Defined by a State-Dependent Ohm's Law

2.2 If It's Pinched It's a Memristor

2.3 Ideal Memristor

3 When is a Memristor Non-volatile?

4 Synapses Are Memristors

4.1 Learning with Memristors: Habituation

4.2 Learning with Memristors: LTP

5 Hodgkin-Huxley Axon is Made of Memristors

5.1 Anomalies of the Hodgkin-Huxley Axon Circuit Model

5.2 Deriving the DC V-I Characteristic of the Hodgkin-Huxley Axon

5.3 Deriving the Small-Signal Admittance of the Hodgkin-Huxley Axon

6 Neurons Are Poised Near the Edge of Chaos

6.1 Eigenvalues of Hodgkin-Huxley Axon Are Zeros of Y(s)

6.2 Action Potential Originates Near the Edge of Chaos

7 How Did I Connect Memristor to Hodgkin-Huxley?

References

11 Brains Are Made of Memristors

1 Introduction

2 Characterization of Pinched Hysteresis Loops

2.1 Examples of Pinched Hysteresis Loops of Potassium Memristor

2.2 Examples of Pinched Hysteresis Loops of Sodium Ion-Channel Memristor

2.3 Computation of Lobe Area of Pinched Hysteresis Loop via Riemann–Stieltjes Integral

2.4 Clockwise and Counter-Clockwise Orientation of the Pinch Hysteresis Loop of a Memristor

3 DC V-I Curves of the Potassium Ion-Channel Memristor, Sodium Ion-Channel Memristor and Memristive Hodgkin-Huxley Axon Circuit Model

4 Small-Signal Equivalent Circuits and Nyquist Plot of Ion-Channel Memristor

4.1 Small-Signal Equivalent Circuit and Nyquist Plot of the Potassium Ion-Channel Memristor

4.2 Small-Signal Equivalent Circuit and Nyquist Plot of the Sodium Ion-Channel Memristor

4.3 Small-Signal Equivalent Circuit and Nyquist Plot of the Hodgkin-Huxley Axon Circuit Model

5 Conclusion

References

12 Synapse as a Memristor

1 Introduction

2 How Do Neurons Work?

2.1 Synapse: Bridge for Neurons

2.2 Gerstner's Pair-Based STDP Model

3 Memristor Acting as a Synapse

3.1 Linares' Pair-Based Memristive STDP Model

3.2 Froemke's Triplet-Based STDP Model

3.3 Conflict with the Triplet Rule

4 Memristor Acting as a More Real Synapse

4.1 Memristive STDP Model with Adaptive Thresholds

4.2 Quantitative Equivalency of the Models

5 Short-Term Plasticity Revisited

References

13 Memristors and Memristive Devices for Neuromorphic Computing

1 Introduction

2 Mathematical Definition

2.1 Memristor - Strict Definition

2.2 Memristive Systems

3 Material Systems

3.1 Cation Migration

3.2 Anion Migration

3.3 Modeling

4 Synaptic Plasticity

4.1 Memristors as Weight Storage

4.2 Synapse Emulation

5 Hardware Topology

5.1 Crossbar Architecture

5.2 Hybrid Memristor/CMOS Circuitry

5.3 Emergent Behavior

6 Conclusion

References

14 Self-organization and Emergence of Dynamical Structures in Neuromorphic Atomic Switch Networks

1 Introduction

2 Emergence of a Complex Neuromorphic Architecture

2.1 Inorganic Synapses

2.2 The Growth of a Concept

2.3 Dynamical Circuits

3 Modelling and Simulation of Atomic Switches: From Nodes to Networks

4 Characterization of the Atomic Switch Network

4.1 Device Activation

4.2 Memristive Properties

4.3 Network Plasticity

4.4 Emergent Properties — Harmonic Generation

4.5 Emergent Properties — Criticality

5 Harnessing System Dynamics

5.1 Resistance Control

5.2 Reservoir Computing

6 Conclusions and Outlook

References

15 Spike-Timing-Dependent-Plasticity with Memristors

1 Introduction

2 STDP

2.1 STDP Versus Anti-STDP

2.2 Additive Versus Multiplicative STDP

3 Memristance

3.1 Memristor Moving-Wall Macro Model for Two-Terminal Devices

3.2 Memristor Filament Model for Two-Terminal Devices

4 Relation Between STDP and Memristance

4.1 Influence of Action Potential Shape

4.2 Wall Model Memristors Implement a Multiplicative Type of STDP

4.3 Filament Model Memristors Implement Additive STDP

5 Connecting Memristors with Spiking Neurons for Asynchronous STDP Learning

5.1 STDP Variations

6 Address Event Representation (AER)

7 Building a Self-learning Visual Cortex with Memristors and STDP-Ready AER Hardware

7.1 Topology of V1 Visual Cortex Layer and Physical Realization

7.2 AER Temporal Difference Retina

7.3 STDP Training Results of V1 Layer

8 Practical Limitations, Realistic Sizes, Pitches, Density, Crosstalk and Power Considerations

9 Conclusions

References

16 Designing Neuromorphic Computing Systems with Memristor Devices

1 Introduction

2 Preliminary

3 Hybrid Spiking-Based Multi-Layered Self-Learning Neuromorphic System Based on Memristor Crossbar Arrays

3.1 Problem and Motivation

3.2 Preliminary

3.3 Design Methodology and Hardware Implementation

3.4 System Evaluation

4 Hardware Implementation of Echo State Networks using Memristor Double Crossbar Arrays

4.1 Problem and Motivation

4.2 Preliminary

4.3 Proposed Architecture and Design Procedure

4.4 System Evaluation

5 Conclusions

References

17 Brain-Inspired Memristive Neural Networks for Unsupervised Learning

1 Introduction

2 RRAM Devices

3 RRAM Synapses

4 RRAM Networks

4.1 Feed-Forward Networks

4.2 Recurrent Neural Networks

5 Conclusions

References

18 Neuromorphic Devices and Networks Based on Memristors with Ionic Dynamics

1 Introduction

2 Ion Motion and Filament Dynamics in Oxide Memristors

2.1 Direct Visualization of Oxygen Ion Motion

2.2 Switching Dynamics in HfO2 Memristors

3 Device Optimizations on 2-Terminal Memristors for Neuromorphic Computing

3.1 Optimization of Weight Tuning Linearity

3.2 Correlation Between Number of Weight States with Oxide Structure

4 Development of Multi-terminal Synaptic Devices

4.1 Physically Evolving Networks Based on Self-organization of Ag Nanoclusters

4.2 3-Terminal Devices Emulating Heterosynaptic Plasticity

5 Neuromorphic Networks Based on Memristors

5.1 Neural Networks Composed of Heterosynaptic Devices with Flexible Learning Scheme

5.2 Tolerance of Intrinsic Device Variation in Fuzzy Restricted Boltzmann Machine Networks

6 Conclusion and Outlook

References

19 Associative Enhancement and Its Application in Memristor Based Neuromorphic Devices

1 Introduction

2 Flux and Continuum Resistance Memristors

3 Heterogeneous Pulse Stimuli Association, Synergy and Emergent Properties

4 Applications of Associative Memory in Neuromorphic Hardware

5 Summary

References

20 Organic Memristive Devices and Neuromorphic Circuits

1 Introduction

2 Architecture and Properties of Organic Memristive Devices

3 Logic Elements with Memory

4 Oscillating Element

5 Circuits with Adaptive and Neuromorphic Properties

6 Stochastic Fibrillar and Self-assembled Networks

7 Conclusion

References

21 Bio-inspired Neural Networks

1 Introduction

2 Biological Mechanisms

2.1 Connectome (Wires and Neurons)

2.2 Synapses (Resistance and Biochemistry)

2.3 Charge Propagation and Re-amplification (Ion Flux)

2.4 Two Protypes of Neurons: Excitatory (Glutamatergic) and Inhibitory (GABAergic) Neurons

2.5 Long-Term Potentiation

2.6 Long-Term Depression

2.7 Spike-Time-Dependent Plasticity

3 Implementations Using Memristive Systems and Conventional Electronics

3.1 (Leaky) Integrate and Fire Model

3.2 Long-Term Depression and Potentiation

3.3 Spike-Time-Dependent Plasticity

3.4 Pavlov's Dog

3.5 Hodgkin-Huxley Model

3.6 Complex Problem Solving Using Memristors

4 Conclusion and Outlook

References

22 Memristor Bridge-Based Artificial Neural Weighting Circuit

1 Introduction

2 Memristors and Memristive Devices

3 Synaptic Multiplication via Memristor Bridge

3.1 Weighting of Input Signals via the Memristor Bridge

4 Memristor-Bridge Neuron

5 Weight Programming in Memristor Bridge Synapses

6 Simulation

6.1 Linearity in Synaptic Weight Programming

6.2 Synaptic Weight (Multiplication) Processing

6.3 Applications

7 Conclusion

References

23 Cellular Nonlinear Networks with Memristor Synapses

1 Introduction

2 Brief Review of Memristor Models

2.1 Generalized BCM and Its Circuit Implementation

3 Memristor Synaptic Weighting Circuits for Neuromorphic Applications

3.1 Synaptic Weighting Circuit

3.2 Simulations

4 Conclusions

References

24 Evolving Memristive Neural Networks

1 Introduction

1.1 Content Overview

2 Background

2.1 Spiking Networks

2.2 Resistive Memory Synapses

2.3 Synaptic Plasticity

3 The System

3.1 Neural Control Architecture

3.2 Benchmark Synapses

3.3 STDP Implementation

4 Genetic Algorithm

4.1 Self-adaptive Mutation

4.2 Topology Mechanisms

4.3 GA Control of Variable Synapses

5 Experimentation

5.1 Test Environment

5.2 Results

6 Conclusions

References

25 Spiking Neural Computing in Memristive Neuromorphic Platforms

1 Introduction

2 Spiking Neural Networks

2.1 Spike Information Coding

2.2 Network Topology

3 Spiking Neuron Model

3.1 Biological, Artificial and Spiking Neuron

3.2 Spiking Neuron

4 Synapse and Learning

4.1 Synapse Model

4.2 Learning and Plasticity

5 Hardware Spiking Neural Network Systems

6 Discussion

6.1 Homeostasis

6.2 Winner-Take-All

7 Conclusion

References

26 Associative Networks and Perceptron Based on Memristors: Fundamentals and Algorithmic Implementation

1 Introduction

2 Crossbar Memory Arrays

3 Associative Memories

3.1 Willshaw Network

3.2 Hopfield Network

4 Perceptron

4.1 Principle of Operation

4.2 Algorithm Implementation

5 Conclusions

References

27 Spiking in Memristor Networks

1 Introduction

2 Single Memristor Spiking Properties

2.1 Properties of Memristor Spikes

2.2 A Mathematical Description of Experimentally-Measured Spikes

2.3 Theoretical Model of Single Spikes

2.4 The Memory-Conservation Theory as Applied to Memristor Spikes

2.5 Conservation Function

3 Constructionist Approach to Memristor Networks

3.1 Methodology

3.2 Two Memristor Circuit Results

3.3 Three Memristor Circuit Results

4 Conclusion

References

28 Three-Dimensional Crossbar Arrays of Self-rectifying Si/SiO2/Si Memristors

1 Introduction

2 Overview of Silicon Oxide Based Memristors

3 Self-rectifying P-Si/SiO2/N–Si Memristors

3.1 Unipolar Resistive Switching in Silicon Oxide

3.2 Room-Temperature Fabrication of Crystalline Silicon Electrode

3.3 Self-rectifying Resistive Switching Behavior

4 Switching Mechanism Study

4.1 Electrical Measurements

4.2 Physical Characterization

5 Three-Dimensional All Silicon Memristors Crossbars

5.1 SPICE Simulation

5.2 Experimental Measurements

6 Conclusions

References

29 The Self-directed Channel Memristor: Operational Dependence on the Metal-Chalcogenide Layer

1 Introduction

2 Materials Modifications

3 Device Structure and Fabrication

4 Electrical Measurements

4.1 DC I-V Measurements of All Samples at Room Temperature

4.2 CW I-V Room Temperature Results

4.3 LT Spice Model Simulations

4.4 DC and Cycling Endurance Measurements at Temperature

4.5 Programmed Resistance as a Function of Temperature

4.6 Endurance Cycling

5 Conclusions

References

30 Resistive Switching Devices: Mechanism, Performance and Integration

1 Resistive Switching Mechanisms

1.1 Electrochemical Metallization (ECM)

1.2 Valence Change Mechanism (VCM)

1.3 Thermochemical Mechanism (TCM)

1.4 Electrostatic/Electronic Effects

1.5 Phase Change Memory Mechanism (PCM)

2 Performance Improvement

2.1 Material Modulation

2.2 Device Structure Design

2.3 Operating Schemes Optimization

3 Integration of Resistive Switching Memory

3.1 Active Array

3.2 Passive Array

3.3 3D Architectures

3.4 Reliability Issue for 3D RRAM Array

References

31 Behavior of Multiple Memristor Circuits

1 Introduction

2 Single Memristor Circuit

2.1 Linear Model

2.2 Nonlinear Model

3 Transient and Stable State of Composite Memristance

4 Composite Memristance of Serially Connected Memristors

4.1 Serial Memristor Circuit with the Same Polarities

4.2 Serial Memristor Circuit with the Opposite Polarities

5 Composite Memristance of Parallel Memristors

5.1 Parallel Memristor Circuit with Identical Polarities

5.2 Parallel Memristor Circuit with Opposite Polarities

6 Simulation Results

6.1 Linear Model

6.2 Nonlinear Model

6.3 Memristance Variance

7 Conclusion

References

32 A Memristor-Based Chaotic System with Boundary Conditions

1 Introduction

2 The HP Memristor Model with Boundary Conditions

3 A New Memristive Chaotic System

4 Chaotic Attractor and its Bifurcation Analysis

5 Analog Implementation and SPICE Simulations of the Chaotic Attractor

6 Conclusions

References

33 Switching Synchronization and Metastable States in 1D Memristive Networks

1 Introduction

2 Accelerated and Decelerated Switching of Memristive Systems

3 Switching Synchronization

3.1 Numerical Results

3.2 Exact Analytical Solution

4 Metastable Memristive Lines

4.1 Numerical Results

4.2 Analytical Modeling

4.3 Application to Logic Gates

References

34 Modeling Memristor–Based Circuit Networks on Crossbar Architectures

1 Introduction

2 Application Potential of Memristor Based Circuits

3 Memristor Device Modeling

3.1 Related Work

3.2 A Novel Memristor Circuit Model

3.3 Verification of the Proposed Model

4 Dynamics of Memristors in Regular Network Connections

4.1 Memristors Connected in Series

4.2 Memristors Connected in Parallel

5 Circuit Design Paradigm

5.1 Implementation of the Universal Digital Logic Gates

5.2 Crossbar Circuit Simulator

5.3 Simulation of Memristor–Based Crossbar Circuits

5.4 Performance Evaluation of Memristor–Based Circuits

6 Conclusions

References

35 Memristive In Situ Computing

1 Introduction

1.1 Uncertainty Mitigation for Cycle-to-Cycle Switching

2 Device Dynamics

3 Analog In Situ Computing

3.1 Muti-stable State

3.2 Plasticity and Learning

3.3 Programmable Analog Circuits

4 Digital In Situ Computing

4.1 Complementary Resistive Switch: Diodeless Nanocrossbars

4.2 CRS-Based Boolean Operations

References

36 Memory Effects in Multi-terminal Solid State Devices and Their Applications

1 Introduction

2 Generalization of the Memristive Devices

2.1 Resistive RAMs

2.2 Mem-Capacitive Switching Devices

2.3 Mem-Inductive Switching Devices

2.4 Three-Terminal Memristive Devices

2.5 Four-Terminal Memristive Devices

3 Applications of Resistive RAMs

3.1 Standalone Memories

3.2 Generic Memory Structure (GMS) for Non-volatile FPGAs

3.3 Resistive Programmable TSVs

4 Applications of Multi-terminal Memristive Devices

4.1 Neuromorphic Circuits

4.2 Current and Temperature Sensor

5 Conclusions

References

37 A Taxonomy and Evaluation Framework for Memristive Logic

1 Introduction

2 Classification of Memristive Logic Families

2.1 Statefulness

2.2 Proximity of Computation

2.3 Flexibility

3 Logic-Enabled Memory and Evaluation Metrics for Memristive Logic Families

3.1 Logic-Enabled Memory

3.2 Evaluation Metrics

4 Latency of Memristive Logic Families

4.1 In-Memory Logic Families

4.2 Near-Memory Logic Families

4.3 Out-of-Memory Logic Families

5 Energy Efficiency of Memristive Logic Families

5.1 Energy of In-Memory Logic Families

5.2 Energy of Near-Memory Logic Families

5.3 Energy of Out-of-Memory Logic Families

6 Area Evaluation of Memristive Logic Families

7 Case Study: Eight-Bit Full Adder Operation

7.1 In-Memory Computing: MAGIC

7.2 Near-Memory Computing: MAJ

7.3 Out-of-Memory Computing: FBLC

8 Evaluation of Eight-Bit Addition Case Study

8.1 Methodology

8.2 MAGIC

8.3 MAJ

8.4 FBLC

8.5 Analysis of Results

9 Single Instruction Multiple Data (SIMD)

10 Conclusions

References

38 Memristive Stateful Logic

1 Introduction

2 Basic Memristive Stateful Logic Operations

2.1 Generalized Stateful Logic

2.2 Keeper Circuits

2.3 Stateful Logic Operations

2.4 Remarks

3 Synthesis of Boolean Functions

3.1 Definitions

3.2 Synthesis Using the Conjunctive Normal Form

3.3 Synthesis Without Complementary Representation of Variables

3.4 Remarks

4 Stateful Logic Within a Memristive Crossbar

4.1 Preventing Sneak Current Paths

4.2 Example on Stateful Logic Within a Memristive Crossbar

5 Concluding Remarks

References

39 Memristor-Based Addition and Multiplication

1 Introduction

2 Previous Research

2.1 Memristor Switch Logic

2.2 Memristors as Analog Memory

2.3 Memristor Interconnect Over CMOS

3 Logic Operations Via Material Implication

4 A Memristor Full Adder

4.1 Full Adder Realized Via Material Implication

5 A Memristor Ripple Carry Adder

5.1 A Ripple Carry Adder Realized Via Material Implication

6 A Memristor Carry Lookahead Adder

7 A Memristor Array Multiplier

8 Conclusions

References

40 Memristor Emulators

1 Memristor Emulator Requirements

2 Analog Emulators of the Memristor

2.1 Mutator-Based Emulators

2.2 Direct-Type Emulators

3 Digital and Hybrid Emulators of Memristors

4 Other Types of Memristor Emulators

5 Future Possible Trends in Memristor Emulation

6 Conclusions

References

41 Computing Shortest Paths in 2D and 3D Memristive Networks

1 Introduction

2 Methodology

2.1 Memristive Components

2.2 Memristive Fuse

2.3 SPICE Simulations

3 Shortest Path Solution of Mazes Using 2D Memristive Networks

4 Multiple Shortest Path Computations Using 2D Memristive Networks

5 Shortest Path Computations Using 3D Memristive Networks

6 Conclusion

References

42 Computing Image and Motion with 3-D Memristive Grids

1 Introduction

2 Background

2.1 Vertebrate's Retina: Architecture and Cells

2.2 Mathematical Model of Memristors

2.3 Optical Flow

3 Biomimetic Outer Plexiform Layer

3.1 Smoothing and Local Gaussian Filtering

3.2 Edge Detection

3.3 Adaptation to Light Conditions

3.4 Fault Tolerance

4 Detecting Moving Edges With Memristive Grids

4.1 Simulation Methods

4.2 Detection of Moving Edges Via Memristive State Thresholding

4.3 Edge Detection Based on Monitoring the Memristance Modulation Rate

4.4 Adaptation to Varying Lighting Conditions

4.5 Memristance Variability Tolerance

5 Double Layered Memristive Network

5.1 Biomimetic OPL and IPL

5.2 Emulating Transient Detection

5.3 Directional and Speed Detection

6 Conclusion

References

43 Solid-State Memcapacitors and Their Applications

1 Introduction

2 Physical Realizations of a Memcapacitor

2.1 Capacitor with Elastic Membrane Electrode

2.2 Capacitor with Multiple Metal and Insulator Layers

2.3 Ferroelectric Capacitor

2.4 Capacitor Appended with Memristive Layer

3 Applications of Memcapacitors

3.1 Device Models

3.2 Memory

3.3 Tunable Analog and Neuromorphic Circuits

3.4 CNN Cell with Memcapacitors

4 Conclusions

References

44 Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors

1 Introduction

2 The Model

3 Dynamic Behaviors of Memristor RD model

3.1 1-D Reaction-Diffusion Medium with Memristors

3.2 2-D Reaction-Diffusion Medium with Memristors

4 Conclusion

References

45 Mimicking Physarum Space Exploration with Networks of Memristive Oscillators

1 Introduction

1.1 Memristors in the Focus

1.2 What Is So Special About Physarum polycephalum?

1.3 Shortest Path and Maze Solving Physarum Computing

2 Physarum-Inspired RLCM Oscillator

2.1 Voltage-Controlled Behavioral Model of a Bipolar Memristor

2.2 Circuit Dynamics and Training

3 Memristive Circuit and System Applications

3.1 Circuit-Level Approach

3.2 System-Level Approach

4 Conclusions

References

46 Autowaves in a Lattice of Memristor-Based Cells

1 Introduction

2 MCNN Model

3 Simulation Results

4 FPGA-Based Implementation of the MCNN

References

47 Memristor Cellular Automata and Memristor Discrete-Time Cellular Neural Networks

1 Introduction

2 Cellular Automata

3 Cellular Neural Networks

4 Memristor

5 Memristor Cell

5.1 Basic Cell

5.2 Logical Operations

5.3 Series Connection of Memristors

5.4 Asynchronous Inputs

6 Memristor Cellular Automaton

6.1 Rule 126 Memristor Cellular Automaton

6.2 Sierpinski Memristor Cellular Automaton

6.3 Totalistic Two-Dimensional Memristor Cellular Automaton

6.4 Horizontal Hole Detection Memristor Cellular Automaton

6.5 Edge Detection Memristor Cellular Automaton

6.6 Erosion

6.7 Dilation

6.8 Laplacian Memristor Cellular Automaton

6.9 Sharpening Filter Memristor Cellular Automaton

6.10 Noise Removal Memristor Cellular Automaton

6.11 Inverse Half-Toning Memristor Cellular Automaton

7 Memristor Cellular Automaton with Inputs

8 Memristor Discrete-Time Cellular Neural Network

8.1 Dilation

8.2 Erosion

8.3 Edge Detection

8.4 Right Edge Detection

8.5 Face-Vase Illusion

8.6 Shadow Projection

8.7 Line Detection

8.8 Selected Objects Extraction

8.9 Filled Contour Extraction

8.10 Horizontal Hole and Vertical Hole Detection

9 Advanced Memristor DTCNN

9.1 Sandpile Cellular Automaton

9.2 Game of Life

9.3 Multitasking Capability

10 Conclusion

References

Index